Design and Analysis of Majority Logic-Based Approximate Adders and Multipliers

As a new paradigm for nanoscale technologies, approximate computing deals with error tolerance in the computational process to improve performance and reduce power consumption. Majority logic (ML) is applicable many emerging nanotechnologies; its basic building block (the 3-input majority voter, MV) has been extensively used digital circuit design. In this paper, designs of adders multipliers based on ML are proposed; proposed utilize compressors reduction circuitry so-called complement bits. An influence factor defined analyzed assess importance different bits depending size multiplier; scheme selection also presented. The evaluated using hardware metrics (such delay gate complexity) as well metrics. Compared other ML-based found technical literature, offer superior performance. Case studies error-resilient applications presented show validity designs.